Product Overview
To service the fast growing market within PDA and cell phone, this smaller chip size is essential. In 2001, ASE licensed Ultra CSP® from Kulicke & Soffa’s Flip Chip Division. ASE also provided several enhanced structures called “aCSP™” by polyimide, PBO, or thicker Cu RDL to meet various customer demands. aCSP™ is a wafer level CSP package that can be Direct Chip Attached to the PCB board without any interposer. Also, aCSP™ provides the shortest electrical path from Al pad to PCB board to enhance the electrical performance. It has been broadly used in portable devices in passives, analog and logic applications, and is extending to RF applications.

Applications of aCSP™ include bluetooth, Wi-Fi, GPS, FM radio, analog devices, microcontrollers, integrated passives, EEPROM, power and voltage regulator, power amplifier and RF devices. End application include cell phones, PDAs and system boards.

Real chip size (smallest, thinnest and lightest)
High density interconnection
High-speed data processing
Batch process- assembly processed in wafer form
Wire-bond type die can be directly switched to aCSP

Product Offering
aCSP: Through Ball Drop Process
WLCSP: Through Ball Printing/Plating Process

Package Level
Precondition JESD22-A113-D (Level1)85°C/85% RH, 260C 168 hours
TCT JESD22-A101-A85°C/85% RH 1000 cycles
PCT JESD22-A102-B121°C/15 psig/100% RH 96 hours
THT JESD22-A101-A85°C/85% RH 168/500/1000 hours
HTST JESD-22-A103-B150°C 1000 hours
Board Level (Contact ASE for further details.)

Advanced Technology under Development
1. Wafer technology: Qualification for 90 and 65nm wafer
2. Ball pitch: 300um
3. Ball size: 150um ball drop
4. Grinding: Die thickness 200um
5. Plated RDL line/width: 10/10um; 6/6um
6. Plated RDL thickness: >=7um
7. Sawing: Laser sawing

For more information, please contact ASE sales office.
2009 ASE Kaohsiung, All rights reserved. Terms of Use