| Overview |
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| Dual-in-Line packages have been an industry standard for many years. The applications are common in consumer products, automotive devices, memory, analog ICs, and microcontrollers. These packages have evolved into a state-of-the-art technology owing to their robust reliability and great improvement on performance. Using PTH (plated through hole) and SMT (surface mount technology) assembly, dual-in-line packages provide an assortment of packaging capabilities, especially in low pin count devices at competitive manufacturing costs. |
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| Features |
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| Pkg Type |
| PDIP/Skinny PDIP/SDIP |
| SOJ |
| SOP |
| TSOP(I) |
| TSOP(II) |
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(1mm=39.37mil; 1mil=25.4um)
| * |
The width of PDIP is the distance from shoulder-to-shoulder. |
| ** |
The overall thickness is the sum of body and stand-off, exclusive of PDIP. In the case of PDIP, the value is the thickness of body. |
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| Reliability Test Plan |
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| All the dual-in-line packages selected for temperature/humidity test and temperature cycles are subject to precondition process per JEDEC moisture LEVEL3 prior to environmental stress. The test criterion is zero defects out of 45 sampling units. |
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| Temp/Humidity test |
85°C/85% RH, 1000 hr. (JEDEC 22-A101) |
| Pressure cooker test |
121°C/100% RH/15 PSIG, 300 hr (JEDEC 22-A102) |
| Temp cyclic test |
-65°C~150°C, 1000 CYCLES (MIL-STD-883-1010.7) |
| High temp storage test |
150°C, 1000 hr. (JEDEC 22-A103) |
| High accelerated stress test |
130°C/85% RH/33.5 PSIA, 100 hr. (JEDEC 22-A110) |
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