| Product Overview |
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Cost savings BGA (CSBGA) is one of two types of cavity-down thermally enhanced BGA offered at ASE. It is designed with the chip seated onto the copper heat sink to absorb the heat easily. This method desensitizes the performance deviation out of the chip size and lowers the thermal resistance of junction-to-case (θJC) which makes the external heat sink or fan work more effectively.
Cavity-Down BGA enhance thermal performance by about 15~20% improvement compared with 4-layer PBGA and by 35% compare with 2-layer PBGA. Electrical performance of Cavity-Down BGA is significant as well. Reasons are attributed to their flexible layout for staggered traces on different layers, shorter VIAS and better shielding effect out of the copper heat sink. With the heat sink covering the signal traces fully, Cavity-Down BGA provides better resistance to external EMI (Electro- Magnetic Interference) noise. |
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| Application |
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Thermally enhanced package design extensive applications include high-speed, high-power semiconductors, such as ASICs, Micro processors, Gate Arrays and DSPs. CSBGA market covers telecom/cellular, laptops/sub-notebooks, PDAs, VME CPU/BUS boards, video GUI and wireless.
Cavity-Down BGA is an excellent solution for graphic, networking & communication ICs with high-power and high-speed quality performances. |
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| Features |
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| Superior thermal performance (>6W) |
| Superior electrical performance |
| Relative low cost with 10 ~ 50% cheaper compare with L2BGA |
| Laminated substrate design with path through hole VIA for low cost saving solution |
| Designed substrate with side wall plating on cavity edge to reduce wire length and increase design density |
| JEDEC MO-192 / MS-034 standard outlines |
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| Reliability |
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| Package Level |
| Test Item |
Reference Standard |
Condition/Duration |
| MSL |
JEDEC22-A103 |
Level 3, 30°C/60% RH, 192 hrs |
| TCT |
JEDEC 22-A104-B |
-55°C to 125°C, 1000 cycles |
| HAST |
JEDEC 22-A118 |
130°C/85% RH, 33.5 psi 96 hrs |
| HTST |
JEDEC 22-A103-B |
150°C, 1000 hrs |
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